Method and apparatus for simultaneous recording and displaying two different video programs

ABSTRACT

A method and apparatus for simultaneously recording and displaying video signals from two different video sources. The apparatus comprises a main channel processing circuit ( 148 ), a second channel processing circuit ( 150 ), and common circuitry ( 152 ). The common circuit comprises a digital video decoder pipe ( 112 ) that decodes both first and second encoded video signals. A PIP picture is produced using a common reference clock that is derived from the first video signal. In a record mode, a second channel clock reference is coupled to the second channel processing circuit to produce a recordable signal using a digital encoder. The recordable signal also forms a PIP picture that is coupled to the main channel processing circuit to produce a PIP picture that is used to monitor the recording process.

BACKGROUND OF THE DISCLOSURE

[0001] 1. Field of the Invention

[0002] The invention relates to signal processing techniques forsimultaneously recording and displaying two video programs.

[0003] 2. Description of the Background Art

[0004] Television viewers have come to desire simultaneously recordingand viewing programs from two different video sources, e.g., a satellitetelevision program and a standard terrestrial broadcast program.However, various video sources produce video signals that have differenthorizontal and vertical synchronization rates. As such, two separatevideo decoder and display generation systems are needed to facilitateviewing one program, while producing an output signal of another programthat can be recorded as a baseband video output as well as viewed in apicture-in-picture (PIP) display (by inserting that baseband videosignal into a standard PIP circuit). Such a system requires the hardwareof two television receivers.

[0005] Therefore, a need exists for a video processing apparatus havinga single video decoder system that is capable of displaying a mainpicture from a first video signal plus producing a recordable signalfrom a second video signal as well as producing a PIP picture formonitoring the recordable signal.

SUMMARY OF THE INVENTION

[0006] The disadvantages associated with the prior systems are overcomeby a method and apparatus for simultaneously recording and displayingvideo signals from two different video sources. The apparatus comprisesa main channel processing circuit, a second channel processing circuit,and common circuitry. The common circuitry comprises a digital videodecoder pipe that decodes both first and second encoded video signals.The main channel processing circuit processes the decoded first videosignal to form a main picture for display. The second channel processingcircuit processes the decoded second video signal to form a PIP picturefor combination with the main picture for display. The PIP picture isproduced using a common reference clock that is derived from the firstvideo signal. In a record mode, a second channel clock reference iscoupled to the second channel processing circuit to produce a recordablesignal using a digital encoder. The recordable signal also forms a PIPpicture that is coupled to the main channel processing circuit toproduce a PIP picture that is used to monitor the recording process.

BRIEF DESCRIPTION OF THE DRAWINGS

[0007]FIG. 1 depicts a block diagram of a video decoder system inaccordance with the present invention;

[0008]FIG. 1a depicts a block diagram of a video decoder system inaccordance with the present invention including the decoder apparatuscontained within a television receiver;

[0009]FIG. 1b depicts a block diagram of a video decoder system inaccordance with the present invention including the decoder apparatuscontained within a video processing device;

[0010]FIG. 2 depicts a detailed block diagram of a video decoderapparatus in accordance with the present invention; and

[0011]FIG. 3 is a table of illustrative signal formats that can beprocessed by the present invention.

[0012] Identical reference numerals have been used, where possible, todesignate identical elements that are common to the figures.

DETAILED DESCRIPTION

[0013]FIG. 1 depicts a block diagram of a video decoder system 50 fordecoding a plurality of video signals from different video sources. Theillustrative embodiment decodes a pair of encoded video signals (video 1and video 2) that are coupled to the system 50. The system 50 usesdecoders that process a pair of signals that have been encoded using forexample the Moving Pictures Expert Group (MPEG) standard. These signalsare received by the video decoder system 50 from any of a satellitetelevision receiver, a high definition television (HDTV) receiver,digital cable receiver, video cassette recorder (VCR) and the like.

[0014] The system 50 comprises a decoder apparatus 100, a display 52(e.g., a television) and a video processing device 58 (e.g., a videocassette recorder). The decoder apparatus 100 receives and decodes bothvideo signals, video 1 and video 2, using common decoding and timingcircuitry to produce a signal for a main picture 54 (e.g., from video 1)and a signal for recording on the video processing device 58 as well asdisplay in a PIP picture 56 (e.g., from video 2). The decoder apparatus100 may be a stand alone apparatus. Alternatively, the decoder apparatus100 may be integrally contained within any of a satellite televisionreceiver, a high definition television (HDTV) receiver, digital cablereceiver, video cassette recorder (VCR) and the like. FIG. 1aillustrates the decoder apparatus 100 contained within a televisionreceiver 60. FIG. 1b illustrates the decoder apparatus 100 containedwithin a video processing device 70. As such, the system 50simultaneously produces a video signal for display and for recording.Thus, the system 50 is capable of monitoring the recordable signal in aPIP picture 56. By using common circuitry to process two video signals,the decoder apparatus 100 is less expensive to manufacture than priordecoder apparatuses.

[0015]FIG. 2 depicts a detailed block diagram of decoder apparatus 100of FIG. 1. Apparatus 100 comprises a main channel processing circuit148, a second channel processing circuit 150, and common circuitry 152.

[0016] Both video signals (video 1 and video 2) are received ascompressed data by the decoder apparatus simultaneously andindependently of one another. The main compressed data is received by amain channel memory buffer 106 and the second channel compressed data isreceived by a second channel memory buffer 136. The main compressed dataand second channel compressed data are provided to an MPEG VideoVariable Length Decoder (VLD) Pipe 104 which decodes the variable lengthcoding of the main and second channel compressed data and feeds thedecoded data signal streams to a common MPEG Video Decoder Pipe 120.Using an interleaving process, the pipe 120 decodes both of the videosignals and provides the decoded main channel video frames to the mainchannel memory buffer 106 and the decoded second channel video frames tothe second channel memory buffer 136. Since the MPEG video decoder pipe120 is shared by the two video signals, the faster of the two decoderates is used to decode both of the signals, i.e., a 60 Hz decode rateis used over a 59.94 Hz decode rate. If both video signals have the samedecode rate, then, of course, the pipe 120 uses the decode rate of thetwo signals. In the case where the decode rates are different, theslower input video stream is processed faster than necessary. As such,the decoding process for the slower stream will occasionally stop toensure that a data underflow condition will not occur in the mainchannel memory buffer 106 or second channel memory buffer 136.

[0017] The buffer 106 and the buffer 136 are coupled to respective firstin, first out (FIFO) memories 108 and 138. The access (read and write)process of both of the FIFO buffers 108 and 138 is controlled by asingle clock generator 122. The clock generator 122 produces a clocksignal derived from a clock signal produced by a reference clockgenerator 124. The clock signal is provided to each FIFO buffer 108 and138 by the clock generator 122. The clock signal produced by thereference clock generator 124 is locked to the main channel timingsignal.

[0018] FIFO 108 is coupled to the main channel format converter 110.FIFO 138 is coupled to second channel format converter 140. The clocksignal produced by the clock generator 122 is also coupled to the mainand second channel format converters 110 and 140. Since the format ofthe input video signals is arbitrary it must be determined if the inputvideo signals are either field pictures or frame pictures. If thepictures are frame pictures, processing of the picture can not beginuntil at least half of the frame picture plus one macroblock row of thepicture is decoded and available in FIFO 108 or 138. While the bottomhalf of the frame picture is being decoded, format conversion may bestarted on the top half of the picture. Regardless of the interleavingorder between video 1 and video 2 decoding and also regardless of thedecode rate chosen, the last line of the bottom half of the picture mustcomplete decoding in time to be used by the format converters 110 and140. To ensure this condition under every circumstance, it may benecessary to have more than half of the frame picture plus onemacroblock row decoded and in memory before starting format conversion.The format converters 110 and 140 consist of horizontal and verticalsample rate converters, also known as digital filters. The output ofeach converter 110 and 140 is coupled to a respective FIFO memory 112and 142. These FIFOs 112 and 142 each buffer the video frames to ensurethat the frames are synchronized with the display timing signals. Accessto FIFOs 112 and 142 are controlled by the clock signal from thereference clock generator 124.

[0019] The reference clock signal from the reference clock generator 124is also coupled to the main raster generator 128. The generator 128produces horizontal (H) and vertical (V) synchronization signals thatfacilitate display of the main picture onto a display such as a cathoderay tube or liquid crystal display. The H and V signals are coupled tothe display generator 116 for controlling the raster scan of the pixeldata. Additionally, the display generator 116 produces on screengraphics that can be recalled from a graphics memory 114 and controlsthe insertion of the PIP picture into the main picture. The display,comprising on-screen graphics, PIP picture and main picture, is coupledto main digital-to-analog converters (DACs) 118 that produce an analogdisplay for viewing on a television screen.

[0020] The PIP picture is generated from FIFO 142 using a clock signalproduced by the reference clock generator 124 that is routed throughswitch 134. The PIP picture is coupled to the graphics generator 116 fordisplay within the main picture.

[0021] When a recording is to be made of the second channel videosignal, a second channel clock generator 126 produces a clock signal forsecond channel signal timing. This generator 126 uses the referenceclock signal from the reference clock generator 124 as a referencesignal for deriving the second channel clock signal because the recordoutput uses NTSC timing while the main, in some cases, uses ATSC (HDTV)timing. Deriving the second channel clock from the reference clockeliminates the need for a second channel clock recovery circuit. Withina small range of tolerance, the first clock and second clock have afrequency of 81 MHz, 13.5 MHz, 80.919 MHZ or 13.5135 MHz. Thesefrequencies are all related to each other by a factor of 6 and/or afactor of 1000/1001. By providing the ability to scale the recoveredfirst channel clock by one or both of these factors, the second channelclock can be derived within 2× the tolerance of the first channelreference clock. If necessary, the accuracy of the second channel clockcan be further refined by monitoring the decoded video buffer level. Thesecond channel clock is coupled through switch 134 to the FIFO 142 andis coupled to the digital encoder 146, i.e., an NTSC encoder, forconverting the digital television signal into a standard analog NTSCsignal for recording. When in a record mode, switch 134 couples thevideo frames from the output of FIFO 142 to digital encoder 146.

[0022] To facilitate digital encoding, the parameters that define thevertical synchronization of the video signal are required. Theparameters for the available second channel signals are stored invertical parameter storage 154. These parameters are coupled to thedigital encoder 146 through the second channel encoder controller 132.This controller produces a vertical start up (V_(start-up)) signal thatis appropriate for the type of second channel signal being processed.V_(main) and V_(internal) are coupled to the digital encoder 146 throughswitch 130. V_(main) is used if the main channel video is selected forthe digital encoder 146, and V_(internal) is used if the PIP channel isselected for the digital encoder 146. Once the vertical start up signalis received by the digital encoder 146, the digital encoder 146 producesan internally generated vertical synchronization signal.

[0023] In the record mode, the apparatus 100 uses two clock signals: onefor main picture generation and one for generating the recordablesignal. In this mode, the video frames of the recordable signal arecoupled to the graphics generator such that the frames are captured fordisplay as a PIP picture. However, since the timing for producing therecordable signal is not correct for producing the main picture, themain and PIP frames are not synchronized. As such, PIP pictures may berepeated or dropped, as appropriate, to achieve a PIP picture. However,dropping or repeating frames in the PIP picture is typically notnoticeable to a viewer.

[0024] Since there is only one reference clock generator, a voltagecontrolled crystal oscillator (VCXO), that produces a reference clockbased upon the decoded video, the second channel clock is based upon thereference clock. However, the clock signal produced by the secondchannel clock generator is varied depending upon the type of secondchannel signal being received. The reference clock is recovered duringtransport layer processing and is based on a 27 MHz reference clock.Each possible raster timing clock is derived from the recovered 27 MHzreference clock.

[0025]FIG. 3 depicts a chart of various clock frequencies that areproduced by the main channel reference clock generator and the secondchannel reference clock generator to facilitate decoding of differenttypes of video signal formats.

[0026] The apparatus inventively uses the second channel processingcircuit to produce both a recordable signal as well as a PIP picture.Also, a number of decoding and timing circuits are shared by both themain and second channel processing circuits. Additionally, common memoryspace can be used for PIP and recordable signal frame buffers.Consequently, the second channel, main and graphics signals may share acommon memory integrated circuit. Such a decoder apparatus design iscost effective.

1. A method of simultaneously recording and viewing a plurality of videosignals comprising the steps of: (a) decoding a first video signal usinga first clock reference signal; (b) decoding a second video signal usingsaid first clock signal when said first and second video signals are tobe displayed as a main picture and a picture in picture (PIP) picture;(c) decoding said second video signal using a second clock signal whensaid first video signal is to be displayed and said second video signalis to be recorded.
 2. The method of claim 1 wherein said step (c)further comprises displaying said second video signal, while recordingsaid second video signal, as a PIP picture.
 3. The method of claim 1wherein said decoding steps (a), (b) and (c) are performed by an encodedvideo decoder pipe.
 4. The method of claim 3 wherein said encoded videodecoder pipe decodes moving pictures expert group (MPEG) encoded videosignals.
 5. The method of claim 1 wherein the second clock signal isderived from the first clock reference signal.
 6. Apparatus forrecording and displaying a plurality of video signals comprising: anencoded video decoder pipe for decoding said plurality of video signals;a main channel processing circuit, coupled to said encoded video decoderpipe, for producing a main picture for display; a second channelprocessing circuit, coupled to said encoded video decoder pipe, forproducing a decoded video signal for recording and for PIP display. 7.The apparatus of claim 6 further comprising: a reference clock generatorcoupled to said main channel processing circuit and said second channelprocessing circuit; and a second channel clock generator coupled to saidsecond channel processing circuit.
 8. The apparatus of claim 7 whereinsaid second channel clock generator derives a second channel clocksignal from a reference clock signal generated by said reference clockgenerator.
 9. The apparatus of claim 6 wherein said second channelprocessing circuit comprises a digital encoder for producing an analogsignal for recording.
 10. The apparatus of claim 9 wherein said digitalencoder produces an internal vertical synchronization signal.
 11. Theapparatus of claim 6, wherein said apparatus is contained within a videoreceiver.
 12. The apparatus of claim 6, wherein said apparatus iscontained within a video processing device.